| Mixed signal option, additional 8 logic channels |
| Vertical system |
| Input channels |
|
8 logic channels (D7 to D0) |
| Arrangement of input channels |
|
assignment of the logic probes to the channels D7 to D0 |
| Input impedance |
|
100 kΩ ± 2 % || ~4 pF (meas.) at probe tips |
| Maximum input frequency |
signal with minimum input voltage swing and hysteresis setting: normal |
300 MHz (meas.) |
| Maximum input voltage |
|
±40 V (Vp) |
| Minimum input voltage swing |
hysteresis small |
300 mV (Vpp) (meas.) |
| hysteresis medium |
800 mV (Vpp) (meas.) |
| hysteresis large |
1500 mV (Vpp) (meas.) |
| Threshold groups |
|
D7 to D0 |
| Threshold level |
range |
–2 V to 8 V in 10 mV steps |
| predefined |
CMOS, TTL, ECL |
| Threshold accuracy |
|
±(100 mV + 3 % of threshold setting) (meas.) |
| Comparator hysteresis |
|
small, medium, large |
| Horizontal system |
| Channel-to-channel skew |
|
max. 1 ns (meas.) |
| Acquisition system |
| Sampling rate |
|
1 Gsample/s for every channel |
| Memory depth |
|
1 Msample for every channel |
| Trigger system |
|
see Trigger system |
| Waveform measurements |
| Measurement sources |
|
all channels from D7 to D0 |
| Automatic measurements |
|
positive pulse width, negative pulse width, period, frequency, burst width, delay, phase, positive duty cycle, negative duty cycle, positive pulse count, negative pulse count, rising edge count, falling edge count, value at the cursor position |
| Additional cursor function |
|
display of decoded parallel bus value at the cursor position |
| Display characteristics |
| Channel activity display |
|
Independent of the scope acquisition, the state (stays low, stays high or toggles) of the channels from D7 to D0 is displayed. |