PERIOD, PULSE WIDTH, DELAY |
Each parameter is variable within 8 overlapping decade ranges with a
vernier providing continuously variable control within each range. |
PERIOD |
Range |
100nsec to 10sec (10MHz to 0·1Hz). |
Jitter |
<0.1%. |
PULSE WIDTH |
Range |
50nsec to 5sec |
Jitter |
<0.1%. |
DELAY |
Range |
50nsec to 5sec |
TRIGGER, GATE |
RUN |
Normal operational mode in which pulses are generated continuously at
0.1Hz to 10MHz. |
TRIGGERED |
DC to 10MHz pulse train in synchronism with external trigger pulses;
pulse width determined by pulse width controls. Trigger can be generated manually from front panel button. |
GATED |
0·1Hz to 10MHz pulse train, parameters set by period and pulse width
controls, starts synchronously with leading edge of gate input. Last pulse
is completed at the end of gating period. Gating signal can be generated
manually from front panel button. |
PULSE MODES |
NORMAL PULSE |
One pulse is generated each period. The delay setting is ignored. |
SQUAREWAVE |
0·1Hz to 10MHz squarewave, frequency set by the period controls.
Pulse width and delay settings ignored.
Mark : Space ratio: 1:1 ±10%. |
DOUBLE PULSE |
A second pulse is generated after a delay set by the delay controls; the
delay is related to the leading edge of the first pulse. |
DELAYED PULSE |
A pulse is generated after a delay set by the delay controls; the delay is
related to rising edge of the trigger signal. |
INPUTS |
GATE/TRIG INPUT |
Frequency range |
DC - 10MHz |
Signal range |
TTL threshold; max. input ±10V. |
Min. pulse width |
>30nsec. |
Input Impedance |
Typically 10kΩ. |
OUTPUTS |
50Ω OUTPUT |
Amplitude |
Two switch selectable ranges of 0·1V - 1·0V and
1V - 10V from 50Ω. (50mV to 500mV and 500mV to
5V into 50Ω). Adjustable within ranges by a single
turn vernier. |
Rise/Fall Times |
Typically 10nsec into 50Ω load. Maximum 15ns. |
Aberrations |
Typically <5% for output set at >20% of range maxi-
mum, into 50Ω. |
AUX OUTPUT |
Duplicates 50Ω output but at a fixed CMOS/TTL level. |
SYNC OUTPUT |
Amplitude |
A positive going pulse at CMOS/TTL level. |
Timing |
Leading edge starts >20nsec before the TTL/50Ω
output transition. |
Duration |
Typically 30nsec. |
COMPLEMENT SWITCH |
Inverts the AUX and 50Ω outputs. |
GENERAL |
Power |
230V or 115V AC nominal 50/60Hz, adjustable inter-
nally; operating range ±14% of nominal; 20VA max. |
Size |
140 x 220 x 230mm (HxWxD) |
Weight |
1.6kg (3.5lb) |
Operating Range |
+ 5°C to 40°C, 20-80% RH. |
Storage Range |
- 40°C to 70°C |
Safety |
Complies with EN61010-1. |
EMC |
Complies with EN55081-1 and EN50082-1. |