Rohde & Schwarz RTO6-B1 Specifications |
Vertical system |
Input channels |
|
16 logic channels (D0 to D15) |
Arrangement of input channels |
|
arranged in two logic probes with 8 channels each, assignment of the logic probes to the channels (D0 to D7 or D8 to D15) is displayed on the probe |
DC input resistance |
at probe tips |
100 kΩ ± 2 % (meas.) |
Input capacitance |
4 pF (meas.) |
Maximum input frequency |
signal with minimum input voltage swing and hysteresis setting: normal |
400 MHz (meas.) |
Maximum input voltage |
|
±40 V (Vp) |
Minimum input voltage swing |
|
500 mV (Vpp) (meas.) |
Threshold groups |
|
D0 to D3, D4 to D7, D8 to D11 and D12 to D15 |
Threshold level |
range |
±8 V in 25 mV steps |
predefined |
CMOS 5.0 V, CMOS 3.3 V, CMOS 2.5 V, TTL, ECL, PECL, LVPECL |
Threshold accuracy |
threshold setting between ±4 V |
±(100 mV + 3 % of threshold setting) (meas.) |
Comparator hysteresis |
|
normal, robust, maximum |
Horizontal system |
Channel deskew |
range for each channel |
±200 ns |
Channel-to-channel skew |
|
< 500 ps (meas.) |
Acquisition system |
Sampling rate |
max. |
5 Gsample/s on each channel |
Realtime waveform acquisition rate |
max. |
> 200 000 waveforms/s |
Memory depth |
at max. sampling rates |
200 Mpoints for every channel |
at lower sampling rates |
100 Mpoints for every channel |
Decimation |
|
pulses lost due to decimation are displayed |
Trigger system |
Holdoff range |
time |
100 ns to 10 s, fixed and random |
events |
1 event to 2,000,000,000 events |
Trigger modes |
Edge |
triggers on specified slope (positive, negative or either) in the source signal |
sources |
any channel from D0 to D15 or any logical combination of D0 to D15 |
Width |
triggers on positive or negative pulse of specified width in the source signal; width can be shorter, longer, equal, inside or outside the interval |
sources |
any channel from D0 to D15 or any logical combination of D0 to D15 |
pulse width |
200 ps to 10 s |
Timeout |
triggers when the source signal stays high, low or unchanged for a specified period of time |
sources |
any channel from D0 to D15 or any logical combination of D0 to D15 |
timeout |
200 ps to 10 s |
Data2clock |
triggers on setup time and hold time violations between a clock signal and a data signal; monitored time interval with a max. width of 200 ns and a position of max. ±1 µs relative to the clock edge |
data signal |
any subset of channels from D0 to D15 or any user-defined bus signal |
clock signal |
any channel from D0 to D15 |
Pattern |
triggers when the source goes true or stays true for a period of time shorter, longer, equal, inside or outside a specified range |
sources |
any logical combination of D0 to D15 or any user-defined bus signal |
pulse width |
200 ps to 10 s |
State |
triggers on the slope (positive, negative or either) of the clock signal when data signal matches a user-defined logical state |
data signal |
any logical combination of D0 to D15 or any user-defined bus signal |
clock signal |
any channel from D0 to D15 |
Serial pattern |
triggers on a serial data pattern of up to 32 bit; pattern bits may be high (H), low (L) or don’t care (X); clock edge slope may be positive, negative or either |
data signal |
any channel from D0 to D15 or any logical combination of D15 to D15 |
clock signal |
any channel from D0 to D15 |
max. data rate |
1 Gbps |
Serial bus trigger |
optional |
see dedicated triggering and decoding options |
sources |
any channel from D0 to D15 |
Waveform measurements |
General features |
|
measurement panels, gate, statistics, long-term analysis and limit check; see features of the base unit |
Measurement sources |
|
all channels from D0 to D15 or any logical combination of D0 to D15 |
Automatic measurements |
|
positive pulse width, negative pulse width, period, frequency, burst width, delay, phase, positive duty cycle, negative duty cycle, positive pulse count, negative pulse count, rising edge count, falling edge count |
Additional cursor function |
|
display of decoded bus value at the cursor position |
Display characteristics |
Display of logical channels |
|
selectable size and position on screen, diagram configuration by dragging and dropping signal icons |
Bus decode |
number of bus signals |
4 |
bus types |
unclocked and clocked |
display types |
decoded bus, logical signal, bus + logical signal, amplitude signal, amplitude + logical signal, tabulated list (decoded time interval selected with cursors) |
position and size |
size and position on screen selectable |
data format of decoded bus |
hex, unsigned integer, signed integer, fractional, binary |
data format of amplitude signal |
unsigned integer, signed integer, fractional, binary offset |
Channel activity display |
|
independent of the oscilloscope acquisition, the state (stays low, stays high or toggles) of the channels from D0 to D15 is displayed in the signal icon |