| I2C triggering and decoding |
| Bus configuration |
sources for SCL and SDA |
| R&S RTM3002 |
channel 1, channel 2, logic channels from D15 to D0 (requires R&S RTM-B1 option) |
| R&S RTM3004 |
channel 1, channel 2, channel 3, channel 4, logic channels from D15 to D0 (with R&S RTM-B1 option) |
| bit rate |
up to 10 Mbps |
| size of address |
7 bit or 10 bit |
| size of data |
8 bit |
| label list |
associate frame identifier with symbolic ID |
| Trigger |
trigger events |
start, stop, restart, missing acknowledge, address (7 bit or 10 bit), data, address and data |
| offset for trigger on data |
0 data byte to 4095 data byte |
| data pattern width |
up to 3 sequential data byte |
| Decode |
displayed signals |
bus signal, logic signal or both |
| color coding of bus signal |
address, data, start, stop, ACK, NACK, error |
| displayed format of address |
hex, symbolic ID (label list) |
| displayed format of data |
ASCII, binary, decimal or hex |
| SPI triggering and decoding |
| Bus configuration |
sources for CS, CLK, MOSI and MISO |
| R&S RTM3002 |
channel 1, channel 2, logic channels from D15 to D0 (requires R&S RTM-B1 option) |
| R&S RTM3004 |
channel 1, channel 2, channel 3, channel 4, logic channels from D15 to D0 (with R&S RTM-B1 option) |
| bit rate |
up to 25 Mbps |
| chip select (CS) |
active low, active high or missing (SSPI) |
| clock (CLK) slope |
rise or fall |
| data symbol size |
1 bit to 32 bit |
| idle time for SSPI |
12.8 ns to 26.8 ms |
| Trigger |
trigger events |
start of frame, end of frame, bit number, data pattern |
| selectable bit number |
0 to 4095 |
| offset for trigger on data pattern |
0 to 4095 bit |
| data pattern size |
1 bit to 32 bit |
| Decode |
displayed signals |
bus signal, logic signal or both |
| color coding of bus signal |
data, start, stop, error |
| displayed format of data |
ASCII, binary, decimal or hex |
| data decoding |
MSB or LSB first |